Services

IC design

I offer front-to-back analog mixed‑signal and RF / mmW IC design services in silicon-based triple-well bulk and twin-well PD- and FD-SOI CMOS, BCD and SiGe:C HBT processes (interested in FinFET and GAAFET, and III-V compound semiconductor D/E-mode GaAs pHEMT, GaN HEMT and InSb DHBT processes), covering ASIC specification, design, verification, layout, packaging and characterization, through ChipDesign B.V. (a private limited liability company according to Belgian law, founded in 2012; VAT number: 0501.767.340):

• ASIC specification: design trade-offs using chain analysis-based partitioning (MathWorks MATLAB & Simulink, Verilog-AMS)
• ASIC design: schematic entry and layout (Cadence Virtuoso and Siemens EDA S-Edit/L-Edit)
  • Analog design: analysis and design of comparators (clocked, hysteretic), level shifters, single-ended output and fully‑differential operational amplifiers (OpAmps), reference oscillators (crystal, relaxation, ring), temperature sensors (complementary-to-absolute-temperature (CTAT), proportional-to-absolute-temperature (PTAT)), references (bandgap, beta multiplier), voltage regulators (Ivanov). Frequency compensation of circuits using negative feedback (Ahuja, Miller, resistor or super source follower insertion). Offset minimization (chopping, auto‑zeroing, correlated double sampling). High-speed techniques (pre-charge) (Cadence Spectre/APS, Siemens EDA Eldo, ngspice, interested in Synopsys HSPICE).
  • Digital design: design (Verilog, VHDL) and synthesis (Cadence Genus, interested in Siemens EDA Questa and Synopsys Design Compiler) Interested in place and route with Cadence Innovus and Synopsys IC Compiler II. Interested in integration of FSMs in power management units and SAR ADCs, integration of decimation filter in Σ/Δ ADC, and integration of serial I/O interface IP cores (MIPI CSI, SPI) and SRAM.
  • Electromagnetic (EM) design: on-chip antenna and passives (balun, coupler, inductor, transformer) design with 2.5D MoM solvers (Cadence EMX, Keysight Momentum, Sonnet).
  • High-voltage design (power management): high speed (high dv/dt) gate driver design for IGBT, SiC and GaN power switches, voltage multiplier rectifier design (AC-DC), 3-phase inverters (DC-AC). Interested in charge pump and LC and SC DC-DC converter design (buck, boost).
  • Mixed-signal design:
    • ADC and DAC design: high‑accuracy ADC design (extended counting, SAR, continuous-time (CT) and discrete‑time (DT) Σ/Δ), high‑speed ADC design (flash, folding, pipeline), DAC design (switched capacitor charge redistribution, current steering). Interested in DDS design. Optimization of accuracy, offset & gain error, integral non-linearity (INL) & differential non-linearity (DNL), signal-to-noise ratio (SNR) & spurious-free dynamic range (SFDR).
    • PLL and synthesizer design: mixed‑signal PLL based integer‑N and fractional‑N synthesizer (phase-frequency detector (PFD), charge pump (CP), loop filter (LPF), voltage-controlled oscillator (VCO), prescaler, multi‑modulus divider (MMD), multi-stage noise shaping (MASH) for fractional‑N). I/Q dividers for 4/8-phase local-oscillator (LO) distribution. Interested in all‑digital PLL (ADPLL). Jitter minimization through retiming.
  • RF/mmW design: Analysis of non-linear RF circuits and cyclo-stationary noise (phase noise, jitter) with HB, and (Q)PSS solvers (Cadence Spectre/RF, Keysight GoldenGate, Siemens EDA Eldo).
    • RF (< 6 GHz): multi‑band and multi‑mode (2G (GMSK, TDD), 3G (WCDMA, FDD) and 4G/5G (OFDM, TDD/FDD)) cellular transceiver design and FEM design, including carrier‑aggregation and MIMO architectures. Interested in GNSS/BT/WiFi connectivity transceiver design and UWB transceiver design.
      • Cellular transceiver design
        • LO (local oscillator): mixed‑signal PLL based integer‑N and fractional‑N synthesizer (PFD, CP, LPF, VCO, prescaler, MMD, MASH (in case of fractional‑N synthesizer)). I/Q dividers for 4/8-phase LO distribution. Interested in ADPLL. Jitter minimization through retiming.
        • RX (receiver): low‑noise and highly linear low‑noise amplifiers (LNAs). Noise-cancelling and translational filtering RX architectures (N-phase passive mixing, trans-impedance amplifier (TIA)) for out-of-band (power amplifier, PA) noise suppression. Interested in DT receiver architectures.
        • TX (transmitter): RF DAC architectures, using Σ/Δ quantization noise shaping and mismatch shaping, digital up-conversion and digital modulation, and directly driving a 50 Ohm load.
      • Cellular front-end module (FEM): antenna matching tuner, duplexer specification (BAW, SAW), LNA, PA with envelope tracking supply, SPnT switches.
    • mmW (> 24 GHz): zero-IF and heterodyne FMCW and pulse‑Doppler radar transceiver design, and VSAT receiver design. T/R module design for pulse‑Doppler radar and mmW 5G base station antennas.
      • Phased array design: active and passive phased array architectures, antenna element and antenna array design, passive antenna gain enhancement using parabolic reflectors (dishes) and microwave lenses.
      • Transceiver and T/R module design: In addition to the above-mentioned RF circuits: attenuators, SiGe:C HBT based Gilbert cell mixers for I/Q modulators and vector modulator phase shifters, multipliers, and true-time delay (TTD) phase shifters.
• ASIC floorplanning for minimal IR drops, L*di/dt kicks and optimal thermal conduction. Triple-well isolation of ground domains to prevent coupling of noise and spurs. ESD-proof pad ring design.
• ASIC verification:
  • Mixed-signal ASIC verification using fast MOS solvers (Cadence Spectre FX, interested in Siemens EDA Analog FastSPICE and Synopsys PrimeSim XA), and AMS solvers (Cadence Xcelium, interested in Synopsys PrimeSim XA-VCS). Waveform analysis and debug with Cadence SimVision/Verisium (digital/AMS) and ViVA (analog/RF), incl. post-processing (FFT, eye diagrams, S-parameter and noise plots). Interested in block modelling with SystemVerilog and test bench creation with UVM.
  • ASIC layout verification (DFM, electromigration, IR drops, isolation) using DRC, LVS, parasitic extraction (Cadence PVS/Pegasus, Siemens EDA Calibre), and EM simulation using aforementioned EM solvers. ASIC yield optimization using foundry-supplied PCM data-based process corners and Monte Carlo simulation of extracted views (Siemens EDA Solido PVTMC Verifier).
• IC package design with quasi-static solvers (Ansys Q3D Extractor) and RF/mmW IC package design and signal integrity analysis of PCB designs with full-wave 3D differential equation (FDTD, FEM) and integral equation (MoM) solvers (Ansys HFSS, Dassault Systèmes CST Studio Suite, Cadence EMX, Keysight Momentum and EMPro, Sonnet).
• On-wafer ASIC characterization, incl. large-signal S-parameter, noise (NF, phase noise), and non-linear measurements (ACPR, CSO, CTB, IP3, P1dB, XMOD). ASIC debugging (FIB).
• ASIC qualification and production testing: test formulation, code review, and result assessment.
• Use of agentic (AI) engineering workflows in VS Code with devcontainers and Anthropic Claude Code, to generate and verify HDL code (Verilog, Verilog-A/AMS, SystemVerilog/UVM) and EDA scripts (Cadence SKILL/Ocean, Tcl, Python).

Sensor design

ChipDesign also provides capacitive and piezoelectric MEMS device design services — accelerometers, gyroscopes, inertial measurement units, microphones, resonators and switches.