ChipDesign — Integrated Circuit & Sensor Design
Analog mixed-signal / RF IC design using state-of-the-art (Bi)CMOS processes
Analog mixed-signal / RF IC design — using state-of-the-art (Bi)CMOS processes
Assembly of SoCs integrating analog mixed-signal, memory and processor IPs
Assembly of SoCs — integration of analog mixed-signal, memory and processor IPs
High-voltage IC design using BCD processes
High-voltage IC design — using BCD processes
MMIC design using GaAs pHEMT and GaN HEMT processes
MMIC design — using GaAs pHEMT and GaN HEMT processes

Open-Source Software

ChipDesign BV uses and contributes to open-source EDA software in order to lower costs.

Digital IP

  1. cdriscv-32s-10 — 32-bit RISC-V Core Subsystem (Variant 1): A 32-bit RISC-V microprocessor core subsystem for safety-critical mixed-signal SoCs (Link).
  2. cdriscv-32s-20 — 32-bit RISC-V Core Subsystem (Variant 2): A higher-performance 32-bit RISC-V core subsystem for safety-critical mixed-signal SoCs. It extends cdriscv-32s-10 with bit-manipulation and compressed instructions (incl. Zcmp), physical memory protection on data and fetch, a standard CLINT, a JTAG TAP with a read-only debug window, end-to-end protection on both TCM bus links and a QSPI-master boot loader from external NOR flash, and includes a timing-closed, LVS-clean full-chip top in an IHP SG13G2 pad ring (Link).
  3. pad-ring-ihp — Pad Ring Generator for IHP SG13G2: A pad ring generator for the IHP SG13G2 0.13 µm BiCMOS process (Link).
  4. sg13g2_stdcell_hv — Thick-Oxide (3.3 V) Standard Cell Library for IHP SG13G2: A thick-oxide (3.3 V) standard cell library for the IHP SG13G2 0.13 µm BiCMOS process (Link).
  5. spi-slave-ihp — SPI Slave IP for IHP SG13G2: A small, synchronous SPI slave IP block implemented in Verilog and converted to GDSII for the IHP SG13G2 0.13 µm BiCMOS process using the open-source LibreLane/OpenROAD RTL-to-GDS flow (Link).

NF2FF

NF2FF is a planar near-field to far-field transformation for near-field antenna measurement setups (Link, MATLAB File Exchange).

rfMaxima

rfMaxima is an RF toolbox for the wxMaxima computer-algebra system. rfMaxima allows for symbolic derivation, as well as numerical evaluation (incl. Bode and Smith-chart plotting), of 2-port network (ABCD, G, InverseABCD, H, S, Y, Z), noise and stability parameters. Derivations are based on the solution of the set of Kirchhoff current- and voltage-law equations representing the 2-port. Expressions can be exported to HTML or TeX. Figures can be exported to EPS or PNG (Link).

  1. ABCD and scattering matrix of a lossy transmission line (Link).
  2. Smith chart plotting (Link).
  3. Constant-k filter section (Link).
  4. Capacitively tuned lossy transformer (Link).
  5. Conductor loss of the TE10 mode in a WR-10 waveguide (Link).
  6. Second-order Butterworth filter in Sallen–Key topology (Link).
  7. Efficiency of a class-D output stage (Link).
  8. Equivalent input noise generators of a bipolar transistor (Link).
  9. Input-referred offset of a differential pair (Link).
  10. Curtice MESFET model (Link).
  11. RF CMOS SPST switch (Link).
  12. Capacitive fixed-fixed beam RF MEMS switch (Link).
  13. AT-cut quartz resonator (Link).
  14. Film bulk acoustic resonator (Link).

Verilog-A RF MEMS Models

The Verilog-AMS models can be used with SPICE solvers for DC, small-signal (AC, S-parameters (SP)) and large-signal (harmonic balance (HB), periodic steady-state (PSS), quasi-periodic steady-state (QPSS)) simulation of analog / RF circuits based on RF MEMS components (Link, v2.0.0 package).

  1. Fixed-fixed beam capacitive switch, switched capacitor or varactor — RF_MEMS_CAPACITOR (AEL, VA).
  2. Cantilever ohmic switch — OHMIC_CANTILEVER_RF_MEMS_SWITCH (AEL, VA).
  3. Fixed-fixed beam resonator — RF_MEMS_RESONATOR (AEL, VA).
  4. Reference oscillator (MEMSXO) based on the fixed-fixed beam resonator (SCS, PNG).
  5. MEMS-scale solver tolerances (to be included before disciplines.vams) (VAMS).